Generally stated, presented herein is a technique for enhanced data transfer in a computing environment, and more particularly, to a multiword data transfer technique employing a multi-mode, shared line buffer coupled to a shared system bus connecting devices of the computing environment.
Full motion video and audio displays based on digital signals have become widely available. While these displays have many advantages, they also often require a massive amount of raw digital data. Because the storage and transmission of digital video and audio signals is central to many applications, and because an uncompressed representation of a video and audio signal requires a large amount of storage, the use of digital compression techniques is vital to this advancing art.
Several international standards for the compression of digital video and audio signals have emerged over the past decade, with more currently under development. These standards apply to algorithms for the transmission and storage of compressed digital data in a variety of applications, including: video-telephony and teleconferencing; high quality digital television transmission on coaxial and fiberoptic networks; as well as broadcast terrestrially and other direct broadcast satellites; and in interactive multimedia products on CD-ROM, digital audio tape, and Winchester disk drives.
Several of these standards involve algorithms based on a common core of compression techniques, e.g., the CCITT (Consultative Committee on International Telegraphy and Telephony) Recommendation H.120, the CCITT Recommendation H.261, and the ISO/IEC MPEG-1 and MPEG-2 Standards. The MPEG algorithms have been developed by the Moving Picture Experts Group (MPEG), part of a joint technical committee of the International Standards Organization (ISO) and the International Electro-technical Commission (IEC). The MPEG Committee has been developing standards for the multiplex, compressed representation of video and associated audio signals.
Briefly summarized, the MPEG-2 standard describes an encoding method that results in substantial bandwidth reduction by a subjective lossy compression followed by a lossless compression. The encoded, compressed digital data is subsequently decompressed and decoded in an MPEG-2 compliant decoder. Video and audio decoding in accordance with the MPEG-2 standard are described in greater detail in commonly assigned U.S. Pat. No. 5,576,765, entitled xe2x80x9cVideo Decoderxe2x80x9d, which is hereby incorporated herein in its entirety.
Audio/video decoders are typically embodied as general or special purpose processors and memory. Decoders that are used with television sets are often referred to in the industry as set-top box (STB) systems.
Stand-alone audio/video decoders currently used in STB systems generally utilize a dedicated interface to a specific transport chip and/or network interface module (NIM). However, as the required utility of these STB systems expands, it is becoming desirable to also interface various external devices to the base integrated system.
In order to support this capability, it is desirable that the integrated system of the set top box system be able to support relatively efficient and high speed communications with the external devices to provide the needed flexibility and function for the STB system. Two such devices which are increasingly required in a set top design are an external high-powered processor and an integrated drive electronics (IDE) storage device (i.e., a disk drive). An external processor can provide additional processing power for demanding software applications, while an IDE device allows increased system storage for features ranging from pc-like applications and games to pseudo-VCR type operations.
A limitation effecting these design scenarios involves data access. Existing data access methods are often slow for the amount of data that has to be moved. For example, typical applications require a processor to directly transfer each word or half word of data. Such a solution has the effect of lowering the effective processor performance, and/or the transfers are typically cumbersome to set up and control. Further, prior implementations typically employ dedicated interfaces for each external device coupled to the integrated system of the STB system.
Therefore, in order to establish commercial advantage, there is a need, for example, for an integrated device for an STB system capable of more efficiently interfacing with external devices for high bandwidth data transfer therebetween. The present invention is directed to meeting this need, as well as to others described herein.
The shortcomings of the prior art are overcome and additional advantages are provided through, e.g., the provision of a method for transferring data between a first device and a second device. The method includes: transferring data between the first device and the second device using a line buffer connected to a shared system bus, the shared system bus coupling the first device and the second device together, the transferring including: (i) transferring data between the line buffer and the dedicated memory of the first device, wherein the first device includes a data transfer controller coupled across a bus interface to the shared system bus, the transferring (i) including using the data transfer controller to transfer data between the dedicated memory and the line buffer across the shared system bus; and (ii) transferring data between the line buffer and the second device across the shared system bus, wherein the transferring (i) precedes the transferring (ii) when data is read from the dedicated memory for output to the second device, and the transferring (ii) precedes the transferring (i) when data is to be written to the dedicated memory from the second device.
In another aspect, present herein is a system for transferring data between a first device and a second device. The system includes means for transferring data between the first device and the second device using a line buffer connected to a shared system bus which couples the first device and second device together. The means for transferring includes: (i) means for transferring data between the line buffer and dedicated memory associated with the first device, wherein the first device includes a data transfer controller coupled across a bus interface to the shared system bus, and the means for transferring (i) includes means for using the data transfer controller to transfer data between the dedicated memory and the line buffer; and (ii) means for transferring data between the line buffer and the second device across a shared system bus. When the transferring (i) precedes the transferring (ii), data is read from the dedicated memory for output to the second device, and when the transferring (ii) precedes the transferring (i) data is written to the dedicated memory from the second device.
In another aspect, a set top box system is provided which includes an integrated system having a direct memory access (DMA) controller, an internal processor, a line buffer, an arbiter, and a bus interface. The DMA controller is coupled to the internal processor and is coupled across the bus interface to a shared system bus. The line buffer and the arbiter are also each coupled to the system bus. The integrated system is connected to a dedicated memory and to a second device. The second device is connected to the integrated system across the shared system bus, while the dedicated memory is local to the integrated system. The second device comprises one of a DMA slave or a DMA master. The line buffer is adapted to function in a first data transfer mode as a DMA master, and a second data transfer mode as a DMA slave, depending upon whether the second device itself comprises a DMA slave or a DMA master, respectively. The line buffer comprises a shared line buffer and is employed in transferring data between the second device and the dedicated memory of the integrated system using two independent transfer operations. The arbiter arbitrates between the DMA controller, line buffer and second device for access to the shared system bus.
In a further aspect, the invention provides at least one program storage device readable by a machine, tangibly embodying at least one program of instructions executable by the machine to perform a method of transferring data between a first device and a second device, and in particular, between dedicated memory of the first device, and the second device. The method includes: transferring data between the first device and the second device using a line buffer connected to a shared system bus, the shared system bus coupling the first device and the second device together, the transferring including: (i) transferring data between the line buffer and dedicated memory of the first device, wherein the first device comprises a data transfer controller coupled across a bus interface to the shared system bus, the transferring (i) including using the data transfer controller to transfer data between the dedicated memory and the line buffer in a single, multiword transfer operation; and (ii) transferring data between the line buffer and the second device across the shared system bus in a second, single multiword data transfer operation. The transferring (i) precedes the transferring (ii) when data is read from the dedicated memory for output to the second device, while the transferring (ii) precedes the transferring (i) when data is to be written to the dedicated memory from the second device.
To restate, presented herein is a data transfer technique which implements, for example, a four word (16 byte) buffer integrated within a set top box system. Since this size matches the cache-line (or line) size of today""s integrated microcontroller it is referred to herein as a xe2x80x9cline bufferxe2x80x9d. Advantageously, the line buffer is configurable to appear, in one mode, as a direct memory access (DMA) device to both a dedicated memory subsystem of the integrated chip and to an external controller (such as an external processor) and, in a second mode, as a DMA device to the dedicated memory subsystem and as an IDE master to an external IDE drive. Setup of the line buffer is relatively simple, and includes setting appropriate direction and mode controls, and then activating the line buffer for operation. Since standard DMA and IDE interfaces can be employed, setup of the IDE device or DMA controller for line buffer operations is accomplished in a similar manner as for any other device. Additionally, once setup is complete, data transfer can proceed as a background operation to any processor activity, thus minimizing the impact on processor availability to run application code.
Advantageously, the present invention facilitates high speed transfers between two devices using, for example, a common DMA controller and bus master exchange protocol. Multi-word data transfers occur between the two devices through the use of two independent transfer operations running on a common transfer (e.g., DMA) controller contained within one of the devices, and a shared storage buffer (i.e., line buffer). In one embodiment, data is transferred to/from dedicated memory of the device having the DMA controller from/to the shared line buffer through the use, for example, of an internal DMA channel. Data is then transferred to/from the second device from/to the shared line buffer. If the second device is a DMA slave, the line buffer itself acts as a DMA master. If the second device is a DMA master, the data is transferred using an external DMA channel of that controller.
Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention.